Statistical analysis of subthreshold leakage current for VLSI circuits

R Rao, A Srivastava, D Blaauw… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
We develop a method to estimate the variation of leakage current due to both intra-die and
inter-die gate length process variability. We derive an analytical expression to estimate the …

Razor: A low-power pipeline based on circuit-level timing speculation

D Ernst, NS Kim, S Das, S Pant, R Rao… - … . 36th Annual IEEE …, 2003 - ieeexplore.ieee.org
With increasing clock frequencies and silicon integration, power aware computing has become
a critical concern in the design of embedded processors and systems-on-chip. One of the …

[HTML][HTML] Basilic vein transposition fistula: a good option for maintaining hemodialysis access site options?

RK Rao, GD Azin, DB Hood, VL Rowe, RD Kohl… - Journal of vascular …, 2004 - Elsevier
PURPOSE: The primary use of autogenous arteriovenous access for chronic hemodialysis
is recommended by the National Kidney Foundation–Dialysis Outcomes Quality Initiative …

Furfural hydrogenation over carbon‐supported copper

RS Rao, RTK Baker, MA Vannice - Catalysis Letters, 1999 - Springer
Furfural hydrogenation over copper dispersed on three forms of carbon – activated carbon,
diamond and graphitized fibers – were studied. Only hydrogenation of the C=O bond to form …

Computing the soft error rate of a combinational logic circuit using parameterized descriptors

RR Rao, K Chopra, DT Blaauw… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
Soft errors have emerged as an important reliability challenge for nanoscale very large
scale integration designs. In this paper, we present a fast and efficient soft error rate (SER) …

Parametric yield estimation considering leakage variability

RR Rao, A Devgan, D Blaauw, D Sylvester - Proceedings of the 41st …, 2004 - dl.acm.org
Leakage current has become a stringent constraint in modern processor designs in addition
to traditional constraints on frequency. Since leakage current exhibits a strong inverse …

Soft error reduction in combinational logic using gate resizing and flipflop selection

RR Rao, D Blaauw, D Sylvester - Proceedings of the 2006 IEEE/ACM …, 2006 - dl.acm.org
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This
paper presents novel circuit optimization techniques to mitigate soft error rates (SER) of …

Statistical estimation of leakage current considering inter-and intra-die process variation

R Rao, A Srivastava, D Blaauw… - Proceedings of the 2003 …, 2003 - dl.acm.org
We develop a method to estimate the variation of leakage current due to both intra-die and
inter-die gate length process variability. We derive an analytical expression to estimate the …

Vibration and stability in the melt blowing process

RS Rao, RL Shambaugh - Industrial & engineering chemistry …, 1993 - ACS Publications
A model has been developed to predict the thermal and mechanical behavior of a polymer
stream after it exits a melt blowing die. The model is a logical extension of the Uyttendaele …

Influence of crystallite size on acetone hydrogenation over copper catalysts

RS Rao, AB Walters, MA Vannice - The Journal of Physical …, 2005 - ACS Publications
Acetone hydrogenation was studied over a family of Cu/SiO 2 catalysts as well as UHP Cu
powder and a Cu chromite catalyst. Oxygen chemisorption via dissociative N 2 O adsorption …